Phase change memory device

ABSTRACT

A phase change memory device includes a signal generator configured to generate first and second sensing and amplifying enable signals which are sequentially activated during an activation period of a word line selection signal and each of which has a certain activation period length, a resistance sensor configured to sense a resistance value by applying a certain operation current to a phase change memory cell corresponding to the word line selection signal during an activation period of the first sensing and amplifying enable signal and a voltage level amplifier configured to logically determine a voltage level of the resistance sensing signal based on a voltage level of a logic reference signal during an activation period of the second sensing.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of Korean Patent Application No.10-2009-0041370, filed on May 12, 2009, the disclosure of which isincorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor design technology, andmore particularly, to a sensing and amplifying circuit included in aphase change memory device and an operation thereof.

Many computer memory technologies have been introduced for storingcomputer programs and data. Such technologies include a dynamic randomaccess memory (DRAM), a static random access memory (SRAM), an erasableprogrammable read only memory (EPROM), and an electrical erasableprogrammable read only memory (EEPROM). Some of memory technologiesrequire an application of a voltage to retain stored data while othersdo not require such a voltage application in retaining stored data.

Lately, the demand of a non-volatile memory has increased due to theadvantage of the non-volatile memory, which allows repetition ofreading/writing data. EEPROM is one type of non-volatile memories.EEPROM uses a floating gate transistor for sustaining electric chargeson an insulated floating gate. Each memory cell may be electricallyprogrammed to “1” or “0” by injecting or removing electric charges to orfrom a floating gate. However, EEPROM has some shortcomings too. Forexample, it is difficult to reduce memory cells of EEPROM in size,EEPROM is comparatively slow to perform a read operation and a programoperation, and EEPROM consumes comparatively large amount of power.

As to another type of non-volatile memory, a phase change memory deviceis formed of material that electrically changes structured statesthereof, each of which represents different electric characteristics.For example, memory devices made of chalcogenide material asgermanium.antimony.tellurium mixture (GST). The GST material may beprogrammed between an amorphous state representing a comparatively highresistivity and a crystalline state representing a comparatively lowresistivity (for example, a resistivity lower than the comparativelyhigh resistivity). The GST material is programmed by heating up the GSTmaterial. A heating temperature and time are decided depending onwhether the GST material is left as an amorphous state or a crystallinestate. The high resistivity and low resistivity denote programmed values“1” and “0”. The programmed values can be sensed by measuring theresistivity of the GST material.

In order to perform a write operation for writing data at the GSTmaterial, that is, for programming the GST material as an amorphousstate or a crystalline state, the structured state of the GST materialis changed by applying a comparatively high current to the GST material.

On the contrary, in order to perform a read operation for reading a datavalue of the programmed GST in the amorphous state or the crystallinestate, the resistance value of the GST material is sensed withoutchanging the structured state of the GST material by applyingcomparatively low current to the GST material.

When a phase change memory device is designed to employ the GST materialto form a memory cell, the phase change memory device includes aplurality of phase change memory cells formed of the GST material in anarray like a typical semiconductor memory device such as a DRAMincluding memory cells formed of capacitors in an array.

That is, the phase change memory device performs data input/outputoperations by selecting one of the plurality of phase change memorycells made of GST material in an array by selection of a word line WLand a bit line BL like a DRAM that performs data input/output operationby selecting one of a plurality of memory cells formed in an arraythrough selection of a word line WL and a bit line BL.

A typical DRAM should be controlled to begin sensing and amplifying dataof a selected cell as soon as a word line WL is activated and to sustainthis state until the word line WL is inactivated. If the typical DRAMterminates sensing and amplifying data of the selected cell while theword line WL is activated, the data of the selected cell may beimpaired. Although the data of selected cell is not broken, refreshcharacteristics may be deteriorated due to lack of charged electriccharge.

As described above, the typical DRAM should continuously retain sensingand amplifying data of a selected cell during the activation period of aword line when data input and output operations are performed byselecting one of a plurality of memory cells in an array.

A phase change memory device may employ the same method of the typicalDRAM, which performs sensing and amplifying data of a selected phasechange memory cell during the activation period of a word line WL whendata is inputted/outputted by selecting one of a plurality of phasechange memory cells in the phase change memory cell. When the phasechange memory device employs this method, the phase change memory devicecan normally perform data input/output operations.

However, since a plurality of phase change memory cells arenon-volatile, the phase change memory unnecessarily wastes power if thephase change memory continuously performs sensing and amplifying data ofa selected phase change memory cell during an activation period of aword line WL when data is inputted/outputted by selecting one of phasechange memory cells as in the typical DRAM.

In order words, since the plurality of phase change memory cells in thephase change memory device are non-volatile, a time required forinputting/outputting data is shorter than a time required for activatinga word line WL. Therefore, if the phase change memory devicecontinuously performs sensing and amplifying data of a selected phasechange memory cell during activation of a word line WL, the phase changememory device unnecessarily wastes power during a time equal to as muchas a difference between the time required for activating a word line WLand the time required for inputting/outputting data.

SUMMARY OF THE INVENTION

An embodiment of the present invention is directed to providing asensing and amplifying circuit of a phase change memory device forindependently deciding a time for sensing and amplifying data of a phasechange memory cell regardless of a time corresponding to an activationperiod of a word line WL.

In accordance with an aspect of the present invention, there is provideda phase change memory device comprising a signal generator configured togenerate first and second sensing and amplifying enable signals whichare sequentially activated during an activation period of a word lineselection signal and each of which has a certain activation periodlength, a resistance sensor configured to sense a resistance value byapplying a certain operation current to a phase change memory cellcorresponding to the word line selection signal during an activationperiod of the first sensing and amplifying enable signal and determine avoltage level of a resistance sensing signal corresponding to the sensedresult and a voltage level amplifier configured to logically determine avoltage level of the resistance sensing signal based on a voltage levelof a logic reference signal during an activation period of the secondsensing and amplifying enable signal and output amplified resistancesensing signals by amplifying the determined voltage level of theresistance sensing signal.

In accordance with another aspect of the present invention, there isprovided a phase change memory device comprising a signal generatorconfigured to generate first and second sensing and amplifying enablesignals which are sequentially activated during an activation period ofa word line selection signal and each of which has a certain activationperiod length, a selected cell resistance sensor configured to sense aresistance value by applying a certain selected cell sensing operationcurrent to a phase change memory cell corresponding to the word lineselection signal during an activation period of the first sensing andamplifying enable signal and decide a voltage level of a resistancesensing signal corresponding to the sensed result, a reference cellresistance sensor configured to sense a resistance value of a referencecell by applying a certain reference cell sensing operation current tothe reference cell during an activation period of the first sensing andamplifying enable signal and decide a voltage level of a logic referencesignal corresponding to the sensed result and a voltage level amplifierconfigured to logically determine a voltage level of the resistancesensing signal based on a voltage level of the logic reference signalduring an activation period of the second sensing and amplifying enablesignal, amplify the voltage level of the resistance sensing signal, andoutput amplified resistance sensing signals.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a circuit diagram illustrating a sensing and amplifyingcircuit of a phase change memory device in accordance with an embodimentof the present invention.

FIG. 1B is a diagram illustrating waveforms of a word line selectionsignal and first and second sensing and amplifying enable signals forcontrolling operation of a sensing and amplifying circuit of a phasechange memory device shown in FIG. 1A.

FIG. 2A is a circuit diagram illustrating a sensing and amplifyingcircuit of a phase change memory device in accordance with anotherembodiment of the present invention.

FIG. 2B is a diagram illustrating waveforms of a word line selectionsignal and first and second sensing and amplifying enable signals forcontrolling operation of a sensing and amplifying circuit of a phasechange memory device shown in FIG. 2A.

DESCRIPTION OF SPECIFIC EMBODIMENTS

Other objects and advantages of the present invention can be understoodby the following description, and become apparent with reference to theembodiments of the present invention.

FIG. 1A is a circuit diagram illustrating a sensing and amplifyingcircuit of a phase change memory device in accordance with an embodimentof the present invention.

Referring to FIG. 1A, the sensing and amplifying circuit of the phasechange memory device according to the present embodiment includes asignal generator 100, a selected cell resistance sensor 120, a referencecell resistance sensor 140, and a voltage level amplifier 160. Thesignal generator 100 generates a first sensing and amplifying enablesignal ASEN1 and a second sensing and amplifying enable signal ASEN2,which are sequentially activated during an activation period of a wordline selection signal WL<sel>. Each of the first and second sensing andamplifying enable signals SAEN1 and SAEN2 has a certain activationperiod length. The selected cell resistance sensor 120 senses aresistance value of a phase change memory cell 126 cellR correspondingto a word line selection signal WL<sel> by applying a selected cellsensing operation current SEL_C_DI to the phase change memory cell 126cellR during an activation period of the first sensing and amplifyingenable signal SAEN1 and decides a voltage level of a resistance sensingsignal R_SENS_SIG corresponding to the sensed result. The reference cellresistance sensor 140 senses a resistance value of a reference cell 146refR by applying a reference cell sensing operation current REF_C_DI tothe reference cell 146 refR during an activation period of the firstsensing and amplifying enable signal SAEN1 and decides a voltage levelof a logic reference signal LOGIC_REF_SIG corresponding to the sensedresult. The voltage level amplifier 160 logically determines a voltagelevel of a resistance sensing signal R_SENS_SIG based on a voltage levelof a logic reference signal LOGIC_REF_SIG during an activation period ofthe second sensing and amplifying enable signal SAEN2 and outputsamplified resistance sensing signals RSA_SIG and RSA_SIG# by amplifyingthe voltage level of the resistance sensing signal R_SENS_SIG.

The signal generator 100 includes a first sensing and amplifying enablesignal generator 102 and a second sensing and amplifying enable signalgenerator 104. The first sensing and amplifying enable signal generator102 generates a first sensing and amplifying enable signal SAEN1 inresponse to a read command RD_CMD during an activation period of a wordline selection signal WL<sel>. The second sensing and amplifying enablesignal generator 104 generates a second sensing and amplifying enablesignal SAEN2 in response to the first sensing and amplifying enablesignal SAEN1 during an activation period of a word line selection signalWL<sel>.

The selected cell resistance sensor 120 includes a phase change memorycell cellR 126, a selected cell current applying unit 122, and aresistance sensing signal voltage level controller 124. The phase changememory cell cellR 126 is connected to a ground voltage terminal VSS inresponse to a word line selection signal WL<sel>. The selected cellcurrent applying unit 122 applies a selected cell sensing operationcurrent SEL_C_DI to the phase change memory cell cellR 126 correspondinga word line selection signal WL<sel> in response to the first sensingand amplifying enable signal SAEN1. The resistance sensing signalvoltage level controller 124 decides a voltage level of a resistancesensing signal R_SENS_SIG based on a resistance value of a phase changememory cell cellR 126 corresponding to a word line selection signalWL<sel>, which is sensed through an operation of the selected cellcurrent applying unit 122.

Also, the selected cell current applying unit 122 includes a selectedcell sensing operation current generator 1224 and a selected cellcurrent path controller 1222. The selected cell sensing operationcurrent generator 1224 generates a selected cell sensing operationcurrent SEL_C_DI in response to the current generation control signalI_GEN_CON. The selected cell current path controller 1222 controlsswitching on/off of a path for transferring the selected cell sensingoperation current SEL_C_DI between the selected cell sensing operationcurrent generator 1224 and a phase change memory cell cellR 126corresponding to a word line selection signal WL<sel> in response to thefirst sensing and amplifying enable signal SAEN1.

Among the constituent elements of the selected cell resistance sensor120, the selected cell current path controller 1222 of the selected cellcurrent applying unit 122 includes an NMOS transistor N1 for controllingcurrent flow from the selected cell sensing operation current generator1224 to a phase change memory cell cellR 126 corresponding to a wordline selection signal WL<sel> in response to the first sensing andamplifying enable signal SAEN1. The NMOS transistor N1 includes a gatefor receiving the first sensing and amplifying enable signal SAEN1, adrain connected to the selected cell sensing operation current generator1224, and a source connected to the phase change memory cell cellR 126.

Among the constituent elements of the selected cell resistance sensor120, the resistance sensing signal voltage level controller 124 includesa dividing resistor 1242 having a certain resistance value and connectedbetween the selected cell sensing operation current generator 1224 andthe selected cell current path controller 1222 and outputs a resistancesensing signal R_SENS_SIG from a node DIV_ND_R disposed between thedividing resistor 1242 and the selected cell current path controller.

Among the constituent elements of the selected cell resistance sensor120, the dividing resistor 124 of the resistance sensing signal voltagelevel controller 124 includes a PMOS transistor P1 having a certainfixed resistance value. The PMOS transistor P1 includes a gate connectedto a ground voltage terminal VSS, a drain connected to the selected cellsensing operation current generator 1224, and a source connected to theselected cell current path controller 1222.

The reference cell resistance sensor 140 includes a reference cell refR146, a reference cell current applying unit 142, and a logic referencesignal voltage level controller 144. The reference cell current applyingunit 142 applies a reference cell sensing operation current REF_C_DI tothe reference cell refR 146 in response to a first sensing andamplifying enable signal SAEN1. The logic reference signal voltage levelcontroller 144 decides a voltage level of a logic reference signalLOGIC_REF_SIG corresponding to a resistance value of the reference cellrefR 146, which is sensed through the operation of the reference cellcurrent applying unit 142.

Among the constituent elements of the reference cell resistance sensor140, the reference cell current applying unit 142 includes a referencecell sensing operation current generator 1424 and a reference cellcurrent path controller 1422. The reference cell sensing operationcurrent generator 1424 generates a reference cell sensing operationcurrent REF_C_DI in response to a current generating control signalI_GEN_CON. The reference cell current path controller 1422 controlsswitching on/off of a path for transferring a reference sensingoperation current REF_C_DI between the reference cell sensing operationcurrent generator 1424 and the reference cell refR 146 in response to afirst sensing and amplifying enable signal SAEN1.

Among the constituent elements of the reference cell resistance sensor140, the reference cell current path controller 1422 of the referencecell current applying unit 142 includes an NMOS transistor N3 forcontrolling the flow of a reference cell sensing operation currentREF_C_DI from the reference cell sensing operation current generator1424 to the reference cell refR 146 in response to the first sensing andamplifying enable signal SAEN1. The NMOS transistor N3 includes a gatefor receiving the first sensing and amplifying enable signal SAEN1, adrain connected to the reference cell sensing operation currentgenerator 1424 and a source connected to the reference cell refR 146.

Among the constituent elements of the reference cell resistance sensor140, the logic reference signal voltage level controller 144 includes adividing resistor 1442 having a certain resistance value and connectedbetween the reference cell sensing operation current generator 1424 andthe reference cell current path controller 1422, and a node DIV_ND_Ldisposed between the dividing resistor 142 and the reference cellcurrent path controller 1422 for outputting a logic reference signalLOGIC_REF_SIG.

Among the constituent elements of the reference cell resistance sensor140, the dividing resistor 1442 of the logic reference signal voltagelevel controller includes a PMOS transistor P2 that may be fixed with acertain resistance value. The PMOS transistor P2 includes a gateconnected to a ground voltage terminal VSS, a drain connected to thereference cell sensing operation current generator 1424, and a sourceconnected to the reference cell current path controller 1422.

The voltage level amplifier 160 includes a first input terminal IND1 forreceiving a logic reference signal LOGIC_REF_SIG and a second inputterminal IND2 for receiving a resistance sensing signal R_SENS_SIG,differentially amplifies the voltage level of the resistance sensingsignal R_SENS_SIG based on a voltage level difference of two receivedsignals, and outputs amplified resistance sensing signals RSA_SIG andRSA_SIG# with the amplified voltage level being sustained during anactivation period of the second sensing and amplifying enable signalSAEN2.

Hereinafter, the configuration of the voltage level amplifier 160 willbe described in more detail. The voltage level amplifier 160 includesNMOS transistors N4 to N7 and PMOS transistors P4 to P7. The NMOStransistor N7 includes a gate connected to the first input terminalIND1, a drain connected to a first middle node MND1, and a sourceconnected to a common node COMN. The NMOS transistor N7 controls anamount of current flowing from the first middle node MND1 to the commonnode COMN in response to a logic reference signal LOGIC_REF_SIG appliedthrough the first input terminal IND1. The NMOS transistor N6 includes agate connected to the second input terminal IND2, a drain connected to asecond middle node MND2, and a source connected to the common node COMN.The NMOS transistor N6 controls an amount of current flowing from thesecond middle node MND2 to the common node COMN in response to aresistance sensing signal R_SENS_SIG applied through the second inputterminal IND2. The NMOS transistor N4 and the PMOS transistor P3 controla voltage level of a second output node OUTD2 in response to a voltagelevel of a first output node OUTD1 that shares charge with the firstmiddle node NMD1 in an initial operation period. The NMOS transistor N5and the PMOS transistor P5 control a voltage level of the first outputnode OUTD1 in response to a voltage level of a second output node OUTD2that shares charge with the second middle node MND2 in an initialoperation period. The PMOS transistor P6 includes a gate receiving asecond sensing and amplifying enable signal SAEN2, a source connected toa supply voltage terminal VDD, and a drain connected to a first outputnode OUTD1. Such a PMOS transistor P6 controls switching on/off ofconnection from the supply voltage terminal VDD to the first output nodeOUTD1 in response to the second sensing and amplifying enable signalSAEN2. The PMOS transistor P4 includes a gate receiving a second sensingand amplifying enable signal SAEN2, a source connected a supply voltageterminal VDD, and a drain connected to a second output node OUTD2. ThePMOS transistor P4 controls switching on/off of connection from thesupply voltage terminal VDD to the second output node OUTD2 in responseto the second sensing and amplifying enable signal SAEN2. The NMOStransistor N8 includes a gate receiving a second sensing and amplifyingenable signal SAEN2, a drain connected to a common node COMN, and asource connected to a ground voltage terminal VSS. The NMOS transistorN8 controls switching on/off of connection from the common node COMN tothe ground voltage terminal VSS in response to the second sensing andamplifying enable signal SAEN2.

In the description of the sensing and amplifying circuit of the phasechange memory device according to the present embodiment, the phasechange memory cell cellR 126 corresponding to the word line selectionsignal WL<sel> was mentioned previously. Although FIG. 1A shows only onephase change memory cell cellR 126, a phase change memory device mayinclude a plurality of phase change memory cells. Accordingly, the phasechange memory cell cellR 126 corresponding to the word line selectionsignal WL<sel> should be understood as one of the plurality of phasechange memory cells, which is selected corresponding to a word lineselection signal WL<sel> for sensing and amplifying corresponding data.

In other words, a phase change memory device includes a plurality ofphase change memory cells on/off-controlled to be connected to a groundvoltage terminal VSS based on a word line selection signal WL<sel>unlike FIG. 1A that shows only one phase change memory cellon/off-controlled based on a word line selection signal WL<sel>.

If a phase change memory device is designed to have a plurality of phasechange memory cells arranged in an array, a signal corresponding to arow address is equivalent to a word line selection signal WL<sel> and asignal corresponding to a column address is equivalent to a firstsensing and amplifying enable signal SAEN1 in the sensing and amplifyingcircuit of the phase change memory device according to the presentembodiment shown in FIG. 1A. That is, since the first sensing andamplifying enable signal SAEN1 is a signal generated in response to aread command RD_CMD, the first sensing and amplifying enable signalSAEN1 is a signal corresponding to a column address. Accordingly, a linetransferring a word line selection signal WL<sel> may be equivalent to aword line and a line transferring a selected cell sensing operationcurrent SEL_C_DI may be equivalent to a bit line.

Although it is not shown in FIG. 1A, a sensing and amplifying circuitaccording to another embodiment of the present invention may have afollowing structure when a phase change memory device includes aplurality of phase change memory cells.

The sensing and amplifying circuit according to another embodimentincludes a plurality of phase change memory cells cellR<0:N>, a signalgenerator 100, a resistance sensor 120, a reference cell resistancesensor 140, and a voltage level amplifier 160. The signal generator 100generate a first sensing and amplifying enable signal SAEN1 and a secondsensing and amplifying enable signal SAEN2, which are sequentiallyactivated in response to read commands RD CMD<0:N> corresponding to acolumn address during an activation period of a word line selectionsignal WL<sel> corresponding to a row address and each having a certainactivation period. The resistance sensor 120 applies a selected cellsensing operation current SEL_C_DI to a phase change memory cellcorresponding to a word line selection signal WL<sel> among theplurality of phase change memory cells cellR<0:N> during an activationperiod of a first sensing and amplifying enable signal SAEN1, senses aresistance value of the phase change memory cell, and decides a voltagelevel of a resistance sensing signal R_SENS_SIG corresponding to thesensed result. The reference cell resistance sensor 140 applies acertain reference cell sensing operation current REF_C_DI to a referencecell refR 146 during an activation period of a first sensing andamplifying enable signal SAEN1, senses a resistance value of thereference cell refR 146, and decides a voltage level of a logicreference signal LOGIC_REF_SIG corresponding to the sensed result. Thevoltage level amplifier 160 logically determines a voltage level of aresistance sensing signal R_SENS_SIG based on a voltage level of thelogic reference signal LOGIC_REF_SIG during an activation period of asecond sensing and amplifying enable signal SAEN2, amplifies the voltagelevel of the resistance sensing signal R_SENS_SIG, and outputs amplifiedresistance sensing signals RSA_SIG and RSA_SIG#.

Although the phase change memory device includes a plurality of phasechange memory cells, the configuration of the sensing and amplifyingcircuit is identical to that shown in FIG. 1A. Accordingly, the detaildescription thereof is omitted.

For illustration purposes, the reference cell refR 146 included in thereference cell resistance sensor 140 is a phase change memory cell thatdetermines a voltage level of a logic reference signal LOGIC_REF_SIG.Although FIG. 1A shows the selected cell resistance sensor 120 thatincludes a number of reference cells that are as many as there are phasechange memory cells because FIG. 1A shows the reference cell as elementscorresponding to the selected cell resistance sensor 120, the phasechange memory device includes significantly less reference cells thanphase change memory cells. That is, logic levels of resistance sensingsignals R_SENS_SIG<0:N> corresponding to a plurality of phase changememory cells are determined based on a logic reference signalLOGIC_REF_SIG having a voltage level decided by a reference cell.

Since the reference cell refR 146 may be used to determine a logicallevel of data stored in a plurality of phase change memory cells, thereference cell refR 146 may be formed by serially connecting a phasechange memory cell storing data of logic high with a phase change memorycell storing data of logic low.

However, it is not necessary to include the reference cell refR 146 asshown in FIG. 1A. Unlike FIG. 1A, a phase change memory device maynormally perform a sensing and amplifying operation without thereference cell resistance sensor 140. The phase change memory device mayreceive a logic reference signal LOGIC_REF_SIG from an external deviceor may generate a logic reference signal LOGIC_REF_SIG using an internalvoltage generating circuit. Further, the logic reference signalLOGIC_REF_SIG may be previously stored in a certain register such asMRS.

A sensing and amplifying circuit of a phase change memory deviceaccording to another embodiment of the present invention may have afollowing structure when the phase change memory device receives a logicreference signal LOGIC_REF_SIG from an external device, when the phasechange memory device generates a logic reference signal LOGIC_REF_SIGusing a voltage generating circuit additionally included therein, orwhen the logic reference signal LOGIC_REF_SIG is previously stored in acertain register such as MRS.

The sensing and amplifying circuit includes a signal generator 100, aresistance sensor 120, and a voltage level amplifier 160. The signalgenerator 100 generates a first sensing and amplifying enable signalSAEN1 and a second sensing and amplifying enable signal SAEN2, which aresequentially activated in an activation period of a word line selectionsignal WL<sel> and each having a certain activation period length. Theresistance sensor 120 applies a certain operation current SEL_C_DI to aphase change memory cell cellR 126 corresponding to a word lineselection signal WL<sel> during an activation period of a first sensingand amplifying enable signal SAEN1, senses a resistance value thereof,and decides a voltage level of a resistance sensing signal R_SENS_SIGcorresponding to the sensed result. The voltage level amplifier 160logically determines a voltage level of a resistance sensing signalR_SENS_SIGN based on a voltage level of a logic reference signalLOGIC_REF_SIG during an activation period of a second sensing andamplifying enable signal SAEN2 and outputs amplified resistance sensingsignals RSA_SIG and RSA_SIG# by amplifying the voltage level of theresistance sensing signal R_SENS_SIGN. The logic reference signalLOGIC_REF_SIG may be inputted from an external device through anadditional input pad or generated by an internal voltage generatingcircuit.

As described above, the sensing and amplifying circuit of the phasechange memory device can normally perform a sensing and amplifyingoperation although the reference cell resistance sensor is not includedin the phase change memory device as shown in FIG. 1A. Since theoperation thereof is identical that described with reference to FIG. 1,detail description thereof is omitted.

FIG. 1B illustrates waveforms of a word line selection signal and firstand second sensing and amplifying enable signals for controllingoperation of a sensing and amplifying circuit of a phase change memorydevice shown in FIG. 1A.

The operation of a sensing and amplifying circuit of a phase changememory device according to an embodiment of the present invention willbe described with reference to FIG. 1B.

Among constituent elements of the signal generator 100, the firstsensing and amplifying enable signal generator 102 activates a firstsensing and amplifying enable signal SAEN1 to logic high in response toa read command RD_CMD after the word line selection signal WL<sel> isactivated to logic high. The first sensing and amplifying enable signalgenerator 102 inactivates the first sensing and amplifying enable signalSAEN1 to logic low after a first time t1 passes after the activationtime of the first sensing and amplifying enable signal SAEN1, which isbefore the word line selection signal WL<sel> is inactivated to logiclow.

When the first sensing and amplifying enable signal SAEN1 is activatedto logic high as described above, the selected cell current applyingunit 122 among the constituent elements of the selected cell resistancesensor 120 applies a selected cell sensing operation current I_GEN_CONto a phase change memory cell cellR 126 corresponding to the word lineselection signal WL<sel>.

If the phase change memory cell cellR 126 corresponding to the word lineselection signal WL<sel> becomes an amorphous state and has acomparatively high resistance value, the high resistance value makes itdifficult for the selected cell sensing operation current I_GEN_CON toflow to a ground voltage terminal VSS through the phase change memorycell cellR 126 corresponding to the word line selection signal WL<sel>.As a result, a voltage level of a resistance sensing signal R_SENS_SIGincreases significantly.

On the contrary, if the phase change memory cell cellR 126 correspondingto the word line selection signal WL<sel> becomes a crystalline stateand has a comparatively low resistance value, the low resistance valuemakes it makes it easier for the selected cell sensing operation currentI_GEN_CON to flow to the ground voltage terminal VSS through the phasechange memory cell cellR 126 corresponding to the word line selectionsignal WL<sel>. As a result, the voltage level of the resistance sensingsignal R_SENS_SIG is increases comparatively slightly.

When the first sensing and amplifying enable signal SAEN1 is activatedto logic high, the reference cell current applying unit 142 among theconstituent elements of the reference cell resistance sensor 140 appliesa reference cell sensing operation current REF_C_DI to a reference cellrefR 146 corresponding to a word line selection signal WL<sel>.

Since the reference cell refR 146 is serially connected to a phasechange memory cell in an amorphous state and a phase change memory cellin a crystalline state, the amplitude of the reference cell sensingoperation current REF_C_DI flowing to the ground voltage terminal VSSthrough the reference cell refR 146 becomes relatively not too high andnot too low. Accordingly, the amplitude of the logic reference signalLOGIC_REF_SIG also becomes relatively not too high and not too low.

As described above, the voltage level of the resistance sensing signalR_SENS_SIG and the voltage level of the logic reference signalLOGIC_REF_SIG should be decided before a second time t2 passes after thefirst sensing and amplifying enable signal SAEN1 is activated to logichigh. When the voltage levels are decided after the second time t2passes, the second sensing and amplifying enable signal SAEN2 isactivated to logic high as shown in FIG. 1B.

In other words, the second sensing and amplifying enable signalgenerator 104 among the constituent elements of the signal generator 100activates a second sensing and amplifying enable signal SAEN2 to logichigh at a second time t2 passed after the first sensing and amplifyingenable signal SAEN1 is activated to logic high. The second time t2 isshorter than the first time t1. Further, the second sensing andamplifying enable signal generator 104 inactivates the second sensingand amplifying enable signal SAEN2 to logic low when a word lineselection signal WL<sel> is inactivated to logic low.

When the second sensing and amplifying enable signal SAEN2 is activatedto logic high as described above, the voltage level amplifier 160decides logic levels of amplified resistance sensing signals RSA_SIG andRSA_SIG#.

In more detail, the voltage level amplifier 160 determines a logic levelof data stored in a phase change memory cell cellR 126 corresponding toa resistance sensing signal R_SENS_SIG as logic high if a voltage levelof a logic reference signal LOGIC_REF_SIG is higher than a logic levelof a resistance sensing signal R-SENS_SIG after the second sensing andamplifying enable signal SAEN2 is activated to logic high. Based on thedetermination result, the voltage level amplifier 160 amplifies thevoltage level of the resistance sensing signal R_SENS_SIG to the supplyvoltage level and outputs the amplified resistance sensing signalsRSA_SIG and RSA_SIG#. That is, a voltage level of a main amplifiedresistance sensing signal RSA_SIG is controlled to be a supply voltageVDD level, and a voltage level of a sub amplified resistance sensingsignal RSA_SIG# is controlled to be a ground voltage VSS level.

The voltage level amplifier 160 determines a logic level of data storedin a phase change memory cell cellR 126 corresponding to a resistancesensing signal R_SENS_SIG when a voltage level of the resistance sensingsignal R_SENS_SIG is lower than a voltage level of a logic referencesignal LOGIC_REF_SIG after the second sensing and amplifying enablesignal SAEN2 is activated to logic high. Accordingly, the voltage levelamplifier 160 amplifies a voltage level of the resistance sensing signalR_SENS_SIG to a ground voltage VSS level and outputs the amplifiedresistance sensing signals RSA_SIG and RSA_SIG#. That is, the voltagelevel of the main amplified resistance sensing signal RSA_SIG iscontrolled to be a ground voltage VSS level and the voltage level of thesub amplified resistance sensing signal RSA_SIG# is controlled to be asupply voltage VDD level.

As described above, the sensing and amplifying circuit according to thepresent embodiment uses the first and second sensing and amplifyingenable signals SAEN1 and SAEN2, which are sequentially activated duringan activation period of a word line selection signal WL<sel> and each ofwhich has a certain activation period length. Therefore, the sensing andamplifying circuit according to the present embodiment consumessignificantly less power by performing operations step-by-step.

In other words, the sensing and amplifying circuit according to thepresent embodiment firstly activates a resistance value sensing blockand performs related operations corresponding to a first sensing andamplifying enable signal SAEN1 which is inactivated comparatively ahead.Then, the sensing and amplifying circuit according to the presentembodiment activates a resistance sensing signal amplifying blockcorresponding to the sensed resistance value comparatively and performsrelated operations corresponding to the second sensing and amplifyingenable signal SAEN2 which is inactivated comparatively later. Therefore,the sensing and amplifying circuit according to the present embodimentactivates the constituent elements thereof during a minimum timerequired to perform related operation regardless of a time for retainingan activation state of a word line selection signal WL<sel>. As aresult, the sensing and amplifying circuit according to the presentembodiment consumes the minimum current.

Therefore, it is possible to minimize current flowing into each of phasechange memory cells in a phase change memory device. It means thatstress applied to each of the phase change memory cells is minimized. Asa result, each of the phase change memory cell may stably operatefurther longer.

However, the voltage level amplifier 160 operates during the activationperiod of the second sensing and amplifying enable signal SAEN2 anddecides logic levels of amplified resistance sensing signals RSA_SIG andRSA_SIG#. The activation the point of time for the second sensing andamplifying enable signal SAEN2 is decided in response to the firstsensing and amplifying enable signal SAEN1 while a word line selectionsignal WL<sel> is activated to logic high. After the second sensing andamplifying enable signal SAEN2 is activated to logic high, the secondsensing and amplifying enable signal SAEN2 sustains the activation stateof logic high until the word line selection signal WL<sel> isinactivated to logic low. Then, the second sensing and amplifying enablesignal SAEN2 is inactivated.

Although the voltage level amplifier 160 does not take a long time toamplify a voltage level of a resistance sensing signal R_SENS_SIG, aperiod of retaining the logic high activation state of the secondsensing and amplifying enable signal SAEN2 is comparatively long.

Since the voltage level amplifier 160 is a latch type, the voltagelevels of the amplified resistance sensing signals RSA_SIG and RSA_SIG#are retained as a sensing amplified state only during the period ofsustaining the logic high activation state of the second sensing andamplifying enable signal SAEN2. Therefore, the period of sustaining thelogic high activation state of the second sensing and amplifying enablesignal SAEN2 is comparatively long.

However, more current the voltage level amplifier 160 consumes, longerthe period of sustaining the logic high activation state of the secondsensing and amplifying enable signal SAEN2 becomes. In order to reducepower consumption slightly more, the voltage level amplifier 160 may bemodified to have a structure shown in FIG. 2A.

FIG. 2A is a circuit diagram illustrating a sensing and amplifyingcircuit of a phase change memory device according to another embodimentof the present invention.

As shown in FIG. 2A, the sensing and amplifying circuit according toanother embodiment of the present invention includes constituentelements identical to those of the sensing and amplifying circuit ofFIG. 1A except a signal generator 200 and a voltage level amplifier 260.

Like the sensing and amplifying circuit of FIG. 1A, the sensing andamplifying circuit of FIG. 2A includes a signal generator 200, aselected cell resistance sensor 220, a reference cell resistance sensor240, and a voltage level amplifier 260.

The selected cell resistance sensor 220 and the reference cellresistance sensor 240 are identical to the selected cell resistancesensor 120 and the reference cell resistance sensor 140 of FIG. 1A.Therefore, detail description thereof is omitted.

Hereinafter, the signal generator 200 will be described with referenceto FIG. 2A. The signal generator 200 includes a first sensing andamplifying enable signal generator 202 and a second sensing andamplifying enable signal generator 204. The first sensing and amplifyingenable signal generator 202 generates a first sensing and amplifyingenable signal SAEN1 in response to a read command RD_CMD during anactivation period of a word line selection signal WL<sel>. The secondsensing and amplifying enable signal generator 204 generates a signalsaving signal SAV_SIG and a second sensing and amplifying enable signalSAEN2 in response to the first sensing and amplifying enable signalSAEN1 during the activation period of the word line selection signalWL<sel>.

Hereinafter, the voltage level amplifier 260 will be described withreference to FIG. 2A. The voltage level amplifier 260 includes a sensingand amplifying unit 262 and a voltage level latch unit 264. The sensingand amplifying unit 262 receives a logic reference signal LOGIC_REF_SIGthrough a first input terminal OUTD1 and a resistance sensing signalR_SENS_SIG through a second input terminal IND2, differentiallyamplifies the resistance sensing signal R_SENS_SIG based on a voltagelevel difference of the received two signals during an activation periodof the second sensing and amplifying enable signal SAEN2 and outputs theamplified resistance sensing signals RSA_SIG and RSA_SIG#. The voltagelevel latch unit 264 latches voltage levels of the amplified resistancesensing signals RSA_SIG and RSA_SIG# in response to a signal savingsignal SAV_SIG that toggles during the activation period of the secondsensing and amplifying enable signal SAEN2.

Hereinafter, the sensing and amplifying unit 262 of the voltage levelamplifier 260 will be described in more detail. The sensing andamplifying unit 262 includes NMOS transistors N4, N5, and N6, and PMOStransistors P3 and P4. The NMOS transistor N5 includes a gate connectedto a first input terminal IND1, a drain connected to a first output nodeOUTD1, and a source connected to a common node COMN. The NMOS transistorN5 controls an amount of current flowing from the first output nodeOUTD1 connected to the drain to the common node COMN connected to thesource in response to a logic reference signal LOGIC_REF_SIG appliedthrough the first input terminal IND1. The NMOS transistor N4 includes agate connected to a second input terminal IND2, a drain connected to asecond output node OUTD2, and a source connected to a common node COMN.The NMOS transistor N4 controls an amount of current flowing from thesecond output node OUTD2 to the common node COMN in response to aresistance sensing signal R_SENS_SIG applied through the second inputterminal IND2. The PMOS transistors P3 and P4 are connected to eachothers in current mirror in order to control voltage levels of a firstoutput node OUTD1 and a second output node OUTD2 in response to avoltage level of the first output node OUTD1. The NMOS transistor N6includes a gate for receiving the second sensing and amplifying enablesignal SAEN2, a drain connected to a common node COMN, and a sourceconnected to a ground voltage terminal VSS. The NMOS transistor N6controls switching on/off of connection of the common node COMN and theground voltage terminal VSS in response to the second sensing andamplifying enable signal SAEN2.

The voltage level amplifier 260 receives a logic reference signalLOGIC_REF_SIG through a first input terminal IND1 and a resistancesensing signal R_SENS_SIG through a second input terminal IND2,differentially amplifies the voltage level of the resistance sensingsignal R_SENS_SIG based on a voltage level difference of the tworeceived signals, latches the amplified voltage level, and outputsamplified resistance sensing signals RSA_SIG and RSA_SIG#.

The voltage level amplifier 260 will be described in more detail. Thevoltage level amplifier 260 includes NMOS transistors N4, N5, N6, andN7, and PMOS transistors P3, P4, P5, and P6. The NMOS transistor N7includes a gate connected to a first input terminal IND1, a drainconnected to a first middle node MND1, and a source connected to acommon node COMN. The NMOS transistor N7 controls an amount of currentflowing from the first middle node to the common node COMN in responseto a logic reference signal LOGIC_REF_SIG applied through the firstinput terminal IND1. The NMOS transistor N6 includes a gate connected toa second input terminal IND2, a drain connected to a second middle nodeMND2, and a source connected to a common node COMN. Such a NMOStransistor N6 controls an amount of current flowing from the secondmiddle node MND2 to the common node COMN in response to a resistancesensing signal R_SENS_SIG applied through the second input terminalIND2. The NMOS transistor N4 and the PMOS transistor P3 control avoltage level of a second output node OUTD2 in response to a voltagelevel of the first output node OUTD1 that shares charge with the firstmiddle node MND1 in an initial operation period. The NMOS transistor N5and the PMOS transistor P5 control a voltage level of a first outputnode OUTD1 in response to a voltage level of a second output node OUTD2that shares charge with the second middle node MND2 in an initialoperation period. The PMOS transistor P6 includes a gate for receiving asecond sensing and amplifying enable signal SAEN2, a source connected toa supply voltage terminal VDD, and a drain connected to a first outputnode OUTD1. The PMOS transistor P6 controls switching on/off ofconnection from the supply voltage terminal VDD to the first output nodeOUTD1 in response to the second sensing and amplifying enable signalSAEN2. The PMOS transistor P4 includes a gate for receiving a secondsensing and amplifying enable signal SAEN2, a source connected to asupply voltage terminal VDD, and a drain connected to a second outputnode OUTD2. Such a PMOS transistor P4 controls switching on/off ofconnection from the supply voltage terminal VDD to the second outputnode OUTD2 in response to the second sensing and amplifying enablesignal SAEN2. The NMOS transistor N8 includes a gate for receiving asecond sensing and amplifying enable signal SAEN2, a drain connected toa common node COMN, and a source connected to a ground voltage terminalVSS. Such an NMOS transistor N8 controls switching on/off of connectionfrom the common node COMN to the ground voltage terminal VSS in responseto the second sensing and amplifying enable signal SAEN2.

FIG. 2B is a diagram illustrating waveforms of a word line selectionsignal and first and second sensing and amplifying enable signals forcontrolling operation of a sensing and amplifying circuit of a phasechange memory device of FIG. 2A.

With reference to FIG. 2B, the operation of a sensing and amplifyingcircuit of a phase change memory device according to an embodiment ofthe present invention shown in FIG. 2A will be described.

Among constituent elements of the signal generator 200, the firstsensing and amplifying enable signal generator 202 activates a firstsensing and amplifying enable signal SAEN1 to logic high in response toa read command RD_CMD after a word line selection signal WL<sel> isactivated to logic high. Then, the first sensing and amplifying enablesignal generator 202 inactivates the first sensing and amplifying enablesignal SAEN1 to logic low after a first time t1 passes after theactivating the first sensing and amplifying enable signal SAEN1, whichis a time before the word line selection signal WL<sel> is inactivatedto logic low.

When the first sensing and amplifying enable signal SAEN1 is activatedto logic high as described above, the selected cell current applyingunit 222 applies a selected cell sensing operation current I_GEN_CON toa phase change memory cell cellR 226 corresponding to a word lineselection signal WL<sel>.

If the phase change memory cell cellR 226 corresponding to the word lineselection signal WL<sel> becomes an amorphous state and has acomparatively high resistance value, the high resistance value makes itdifficult for the selected cell sensing operation current I_GEN_CON toflow to a ground voltage terminal VSS through the phase change memorycell cellR 226 corresponding to the word line selection signal WL<sel>as much as the high resistance value. Accordingly, the voltage level ofthe resistance sensing signal R_SENS_SIG increases significantly.

On the contrary, if a phase change memory cell cellR 226 correspondingto a word line selection signal WL<sel> becomes a crystalline state andhas a comparatively low resistance value, the low resistance value makeit easier for the selected cell sensing operation current I_GEN_CON toflow to the ground voltage terminal VSS through the phase change memorycell cellR 226 corresponding to the word line WL<sel>. Accordingly, thevoltage level of the resistance sensing signal R_SENS_SIG increasesslightly.

If the first sensing and amplifying enable signal SAEN1 is activated tologic high, the reference cell current applying unit 242 applies thereference cell sensing operation current REF_C_DI to a reference cellrefR 246 corresponding to a word line selection signal WL<sel>.

Since the reference cell refR 246 is serially connected to a phasechange memory cell in an amorphous state and a phase change memory cellin a crystalline state, the reference cell sensing operation currentREF_C_DI flowing to the ground voltage terminal VSS through thereference cell refR 246 has a certain amplitude which is relatively nottoo high and not too low. Therefore, the logic reference signalLOGIC_REF_SIG always has a certain voltage level that is relatively nottoo high and not too low.

As described above, the voltage levels of the resistance sensing signalR_SENS_SIG and the logic reference signal LOGIC_REF_SIG should bedecided before a second time t2 passes after a first sensing andamplifying enable signal SAEN1 is activated to logic high. When thevoltage levels of the resistance sensing signal R_SENS_SIG and the logicreference signal LOGIC_REF_SIG are decided after the second time t2passes, a second sensing and amplifying enable signal SAEN2 is activatedto logic high as shown in FIG. 2B.

That is, among the constituent elements of the signal generator 200, thesecond sensing and amplifying enable signal generator 204 activates asecond sensing and amplifying enable signal SAEN2 to logic high as soonas a second time t2 passed after a first sensing and amplifying enablesignal SAEN1 is activated to logic high. Here, the second time t2 isshorter than the first time t1. In response to the activation of thesecond sensing and amplifying enable signal SAEN2, a signal savingsignal SVA_SIG is toggled and instantly activated to logic high. Then,the signal saving signal SAV_SIG is inactive to logic low. In responseto the inactivation of the signal saving signal SAV_SIG, the secondsensing and amplifying enable signal SAEN2 is inactivated to logic low.

Therefore, among constituent elements of the voltage level amplifier260, the sensing and amplifying unit 262 amplifies voltage levels ofamplified resistance sensing signals RSA_SIG and RSA_SIG# while thesecond sensing and amplifying enable signal SAEN2 sustains theactivation state as logic high. The voltage level latch unit 264 latchesthe voltage levels of amplified resistance sensing signals RSA_SIG andRSA_SIG# in response to the signal saving signal SAV_SIG toggled whilethe second sensing and amplifying enable signal SAEN2 sustains theactivation state as logic high.

A point of time for inactivating the second sensing and amplifyingenable signal SAEN2 to logic low is not related to a point of time forinactivating a word line selection signal WL<sel> to logic low exceptthat the point of time for inactivating the second sensing andamplifying enable signal SAEN2 is ahead the point of time forinactivating a word line selection signal WL<sel>.

The points of time are not related to each other because the secondsensing and amplifying enable signal SAEN2 is inactivated to logic lowand the sensing and amplifying unit 262 does not operate any more afterthe voltage level latch unit 264 latches the voltage levels of theamplified resistance sensing signals RSA_SIG and RSA_SIG#.

In more detail, among the constituent elements of the voltage levelamplifier 260, the sensing and amplifying unit 262 determines a logiclevel of data stored in a phase change memory cell cellR 226corresponding to a resistance sensing signal R_SENS_SIG as logic high ifa voltage level of a resistance sensing signal R_SENS_SIG is higher thana voltage level of a logic reference signal LOGIC_REF_SIG while thesecond sensing and amplifying enable signal SAEN2 is activated to logichigh. Accordingly, the sensing and amplifying unit 262 amplifies avoltage level of a resistance sensing signal R_SENS_SIG to a supplyvoltage VDD level and outputs amplified resistance sensing signalsRSA_SIG and RSA_SIG#. That is, the sensing and amplifying unit 262controls a voltage level of a main amplified resistance sensing signalRSA_SIG to a supply voltage VDD level and controls a voltage level of asub amplified resistance sensing signal RSA_SIG# to a ground voltage VSSlevel.

Among the constituent elements of the voltage level amplifier 260, thevoltage level latch unit 264 latches the amplified resistance sensingsignals RSA_SIG and RSA_SIG# from the sensing and amplifying unit 262and outputs the latched signals. Here, the voltage level latch unit 264controls the voltage level of main amplified resistance sensing signalRSA_SIG to be the supply voltage VDD level and controls the voltagelevel of sub amplified resistance sensing signal RSA_SIG# to be theground voltage VSS level.

Among the constituent elements of the voltage level amplifier 260, thesensing and amplifying unit 262 determines a logic level of data storedin a phase change memory cell cellR 226 corresponding to a resistancesensing signal R_SENS_SIG as logic low when a voltage level of theresistance sensing signal R_SENS_SIG is lower than a voltage level of alogic reference signal LOGIC_REF_SIG after the second sensing andamplifying enable signal SAEN2 is activated to logic high. Accordingly,the sensing and amplifying unit 262 amplifies a voltage level of theresistance sensing signal R_SENS_SIG to a ground voltage VSS level andoutputs amplified resistance sensing signals RSA_SIG and RSA_SIG#. Thatis, the sensing and amplifying unit 262 controls the voltage level ofthe main amplified resistance sensing signal RSA_SIG to be the groundvoltage VSS level and controls the voltage level of the sub amplifiedresistance sensing signal RSA_SIG# to be a supply voltage VSS level.

Among the constituent elements of the voltage level amplifier 260, thevoltage level latch unit 264 latches the amplified resistance sensingsignals RSA_SIG and RSA_SIG# from the sensing and amplifying unit 262and outputs the latched signals. That is, the voltage level latch unit264 controls the voltage level of the main amplified resistance sensingsignal RSA_SIG to be a ground voltage VSS level and controls the voltagelevel of the sub amplified resistance sensing signal RSA_SIG# to be asupply voltage VDD level.

Among the constituent elements of the voltage level amplifier 260, thesensing and amplifying unit 262 does not perform any operationsregardless of the voltage level of the resistance sensing signalR_SENS_SIG while the second sensing and amplifying enable signal SAEN2is inactivated to logic low and sustains the voltage levels of theamplified resistance sensing signals RSA_SIG and RSA_SIG# as an initialstate. That is, the sensing and amplifying unit 262 controls the voltagelevels of the main and sub amplified resistance sensing signals RSA_SIGand RSA_SIG# to be a supply voltage VDD level.

Among the constituent elements of the voltage level amplifier 260, thevoltage level latch unit 264 does not perform any operations because asignal saving signal SAV_SIG is continuously sustained at a logic lowstate. That is, the voltage level latch unit 264 outputs the latchedamplified resistance sensing signals RSA_SIG and RSA_SIG#, which werelatched when the signal saving signal SAV_SIG is activated to logichigh.

Since the sensing and amplifying circuit of the phase change memorydevice shown FIG. 2A further includes constituent elements for latchingthe independently sensed and amplified resistance sensing signalsRSA_SIG and RSA_SIG# unlike the sensing and amplifying circuit of FIG.1A, a point of time for inactivating the second sensing and amplifyingenable signal SAEN2 to logic low is not necessary to be identical to apoint of time for inactivating a word line selection signal WL<sel> tologic low.

Therefore, the sensing and amplifying circuit of FIG. 2A advantageouslyconsumes less power than the sensing and amplifying circuit of FIG. 1A.However, the sensing and amplifying circuit of FIG. 2A also has someshortcomings. The sensing and amplifying circuit of FIG. 2A occupies alarger area because the sensing and amplifying circuit of FIG. 2Afurther includes constituent elements for latching the sensed andamplified resistance sensing signals RSA_(—) SIG and RAS_SIG#.

As described above, the sensing and amplifying circuit according to thepresent embodiment consumes significantly less power by performing theoperations step-by-step using the first and second sensing andamplifying enable signals SAEN1 and SAEN2, which are sequentiallyactivated while a word line selection signal WL<sel> is activated tologic high and each of which has a certain activation period length.

In other words, the sensing and amplifying circuit according to thepresent embodiment firstly activates a resistance value sensing blockand performs related operation corresponding to a first sensing andamplifying enable signal SAEN1 which is inactivated comparatively ahead.Then, the sensing and amplifying circuit according to the presentembodiment activates a voltage level amplifying block for amplifying avoltage level of a resistance sensing signal R_SENS_SIG corresponding tothe sensed resistance value and performs related operationscorresponding to the second sensing and amplifying enable signal SAEN2which is inactivated comparatively later. Therefore, the sensing andamplifying circuit according to the present embodiment activates theconstituent elements thereof for a minimum time duration of performingrelated operation regardless of a period of retaining an activationstate of a word line selection signal WL<sel>. As a result, the sensingand amplifying circuit according to the present embodiment consumes theminimum current.

Therefore, it is possible to minimize current flowing into each of phasechange memory cells in a phase change memory device. It means thatstress applied to each of the phase change memory cells is minimized. Asa result, each of the phase change memory cell may stably operatelonger.

As described above, the sensing and amplifying circuit according to thepresent embodiment consumes significantly less power by performing theoperations step-by-step using the first and second sensing andamplifying enable signals SAEN1 and SAEN2, which are sequentiallyactivated while a word line selection signal WL<sel> is activated tologic high and each of which has a certain activation period length.

Therefore, it is possible to minimize current flowing into each of phasechange memory cells even during an activation period of a word line.Accordingly, stress applied to each of the phase change memory cells isminimized.

While the present invention has been described with respect to thespecific embodiments, it will be apparent to those skilled in the artthat various changes and modifications may be made without departingfrom the spirit and scope of the invention as defined in the followingclaims.

For example, the sensing and amplifying circuit according to theembodiments were described to use two sensing and amplifying enablesignals for perform operations step-by-step. However, the presentinvention is not limited thereto. The sensing and amplifying circuitaccording to the present invention may use more than two sensing andamplifying enable signals.

Transistors may be modified in location and type according to polarityof an input signal.

1-5. (canceled)
 6. The phase change memory device comprising: a signalgenerator configured to generate first and second sensing and amplifyingenable signals which are sequentially activated during an activationperiod of a word line selection signal and each of which has a certainactivation period length; a resistance sensor configured to sense aresistance value by applying a certain operation current to a phasechange memory cell corresponding to the word line selection signalduring an activation period of the first sensing and amplifying enablesignal and determine a voltage level of a resistance sensing signalcorresponding to the sensed result; and a voltage level amplifierconfigured to logically determine a voltage level of the resistancesensing signal based on a voltage level of a logic reference signalduring an activation period of the second sensing and amplifying enablesignal and output amplified resistance sensing signals by amplifying thedetermined voltage level of the resistance sensing signal, wherein thevoltage level amplifier receives the logic reference signal through afirst input terminal and receives the resistance sensing signal througha second input terminal, and wherein the voltage level amplifierincludes: a sensing and amplifying unit configured to differentiallyamplify a voltage level of the resistance sensing signal based on avoltage level difference of the logic reference signal and theresistance sensing signal during an activation period of the secondsensing and amplifying enable signal and output the amplified resistancesensing signals; and a voltage level latch unit configured to latchvoltage levels of the amplified resistance sensing signals in responseto a signal saving signal that toggles during the activation period ofthe second sensing and amplifying enable signal.
 7. The phase changememory device of claim 6, wherein the signal generator includes: a firstsensing and amplifying enable signal generator configured to generatethe first sensing and amplifying enable signal in response to a readcommand during the activation period of the word line selection signal;and a second sensing and amplifying enable signal generator configuredto generate the signal saving signal and the second sensing andamplifying enable signal in response to the first sensing and amplifyingenable signal during the activation period of the word line selectionsignal.
 8. The phase change memory device of claim 7, wherein the firstsensing and amplifying enable signal generator activates the firstsensing and amplifying enable signal in response to read command afterthe word line selection signal is activated, and wherein the firstsensing and amplifying enable signal generator inactivates the firstsensing and amplifying enable signal after a first time passes after thefirst sensing and amplifying enable signal is activated, which is beforethe word line selection signal is inactivated.
 9. The phase changememory device of claim 8, wherein the second sensing and amplifyingenable signal generator activates the second sensing and amplifyingenable signal after a second time passes after the first sensing andamplifying enable signal is activated where the second time is shorterthan the first time, wherein the second sensing and amplifying enablesignal generator toggles the signal saving signal in response to theactivation of the second sensing and amplifying enable signal, andwherein the second sensing and amplifying enable signal generatorinactivates the second sensing and amplifying enable signal when thetoggling of the signal saving signal is terminated before the word lineselection signal is inactivated. 10-21. (canceled)
 22. The phase changememory device comprising: a signal generator configured to generatefirst and second sensing and amplifying enable signals which aresequentially activated during an activation period of a word lineselection signal and each of which has a certain activation periodlength; a selected cell resistance sensor configured to sense aresistance value by applying a certain selected cell sensing operationcurrent to a phase change memory cell corresponding to the word lineselection signal during an activation period of the first sensing andamplifying enable signal and decide a voltage level of a resistancesensing signal corresponding to the sensed result; a reference cellresistance sensor configured to sense a resistance value of a referencecell by applying a certain reference cell sensing operation current tothe reference cell during an activation period of the first sensing andamplifying enable signal and decide a voltage level of a logic referencesignal corresponding to the sensed result; and a voltage level amplifierconfigured to logically determine a voltage level of the resistancesensing signal based on a voltage level of the logic reference signalduring an activation period of the second sensing and amplifying enablesignal, amplify the voltage level of the resistance sensing signal, andoutput amplified resistance sensing signals, wherein the voltage levelamplifier includes: a sensing and amplifying unit configured to receivethe logic reference signal through a first input terminal, receive theresistance sensing signal through a second input terminal, and outputthe amplified resistance sensing signals by differentially amplifying avoltage level of the resistance sensing signal based on the voltagelevel difference during the activation period of the second sensing andamplifying enable signal; and a voltage level latch unit configured tolatch voltage levels of the amplified resistance sensing signals inresponse to a signal saving signal toggling during the activation periodof the second sensing and amplifying enable signal.
 23. The phase changememory device of claim 22, wherein the signal generator includes: afirst sensing and amplifying enable signal generator configured togenerate the first sensing and amplifying enable signal in response to aread command during an activation period of the word line selectionsignal; and a second sensing and amplifying enable signal generatorconfigured to generate the signal saving signal and the second sensingand amplifying enable signal in response to the first sensing andamplifying enable signal during the activation period of the word lineselection signal.
 24. The phase change memory device of claim 23,wherein the first sensing and amplifying enable signal generatoractivates the first sensing and amplifying enable signal in response tothe read command after the word line selection signal is activated, andwherein the first sensing and amplifying enable signal generatorinactivates the first sensing and amplifying enable signal after a firsttime passes after the first sensing and amplifying enable signal isactivated, which is before the word line selection signal isinactivated.
 25. The phase change memory device of claim 24, wherein thesecond sensing and amplifying enable signal generator activates thesecond sensing and amplifying enable signal after a second time passesafter the first sensing and amplifying enable signal is activated wherethe second time is shorter than the first time, wherein the secondsensing and amplifying enable signal generator toggles the signal savingsignal in response to the activation of the second sensing andamplifying enable signal, and wherein the second sensing and amplifyingenable signal generator inactivates the second sensing and amplifyingenable signal when the toggling of the signal saving signal isterminated before the word line selection signal is inactivated. 26-35.(canceled)